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  • PDFassigments\\assigment1\\/PS1.pdf126.12KB
  • PDFassigments\\assigment1\\/PS1_Solutions_all.pdf1.69MB
  • PDFassigments\\assigment1\\/PS1A.pdf798.11KB
  • PDFassigments\\assigment2\\/PS2.pdf137.01KB
  • PDFassigments\\assigment2\\/PS2_Solutions_all.pdf788.25KB
  • PDFassigments\\assigment3\\/PS3.pdf174.41KB
  • PDFassigments\\assigment3\\/PS3_Solutions.pdf130.71KB
  • PDFassigments\\assigment4\\/PS4.pdf163.25KB
  • PDFassigments\\assigment4\\/PS4_Solutions_all.pdf358.08KB
  • PDFassigments\\assigment4\\/PS4A.pdf250.13KB
  • PDFassigments\\assigment5\\/PS5.pdf175.04KB
  • PDFassigments\\assigment5\\/PS5_Solutions.pdf867.75KB
  • PDFassigments\\assigment5\\/PS5A.pdf551.51KB
  • MP4lectures\\01-Introduction\\/Computer Architecture 0.0 L00-S1Course Introduction.mp499.41MB
  • MP4lectures\\02-Instruction-Set-Architecture-Microcode\\/Computer Architecture 1.0 L1S1 Course Overview (434).mp418.16MB
  • MP4lectures\\02-Instruction-Set-Architecture-Microcode\\/Computer Architecture 1.1 L1S2 Motivation (10).mp495.04MB
  • MP4lectures\\02-Instruction-Set-Architecture-Microcode\\/Computer Architecture 1.2 L1S3 Course Content (910).mp425.75MB
  • MP4lectures\\02-Instruction-Set-Architecture-Microcode\\/Computer Architecture 1.3 L1S4 Architecture and Microarchitecture (2337).mp452.83MB
  • MP4lectures\\02-Instruction-Set-Architecture-Microcode\\/Computer Architecture 1.4 L1S5 chine Models (1602).mp432.83MB
  • MP4lectures\\02-Instruction-Set-Architecture-Microcode\\/Computer Architecture 1.5 L1S6 ISA Characteristics (2547).mp458.02MB
  • MP4lectures\\02-Instruction-Set-Architecture-Microcode\\/Computer Architecture 1.6 L1S7 Recap (0117).mp41.92MB
  • MP4lectures\\03-Pipelining-Review\\/Computer Architecture 2.0 L2S1 Microcoded Microarchitecture (1408).mp481.87MB
  • MP4lectures\\03-Pipelining-Review\\/Computer Architecture 2.1 L2S2 Pipeline Basics (3051).mp464.69MB
  • MP4lectures\\03-Pipelining-Review\\/Computer Architecture 2.2 L2S3 Structural Hazard (1013).mp423.16MB
  • MP4lectures\\03-Pipelining-Review\\/Computer Architecture 2.3 L2S4 Data Hazards (4633).mp492.93MB
  • MP4lectures\\04-Cache-Review\\/Computer Architecture 3.0 L3S1 Control Hazards Jumps (1556).mp426.94MB
  • MP4lectures\\04-Cache-Review\\/Computer Architecture 3.1 L3S2 Control Hazards Branch (2402).mp447.51MB
  • MP4lectures\\04-Cache-Review\\/Computer Architecture 3.2 L3S3 Control Hazards Others(751).mp415.59MB
  • MP4lectures\\04-Cache-Review\\/Computer Architecture 3.3 L3S4 Memory Technologies (2247).mp450.50MB
  • MP4lectures\\04-Cache-Review\\/Computer Architecture 3.4 L3S5 Motivation for Caches (2225).mp4127.36MB
  • MP4lectures\\05-Superscalar1\\/Computer Architecture 4.0 L4S1 Classifying Caches (2807).mp4159.71MB
  • MP4lectures\\05-Superscalar1\\/Computer Architecture 4.1 L4S2 Cache Perfornce (1711).mp431.28MB
  • MP4lectures\\05-Superscalar1\\/Computer Architecture 4.2 L4S3 Superscalar 1 (2).mp413.47MB
  • MP4lectures\\05-Superscalar1\\/Computer Architecture 4.3 L4S4 Basic Two-way In-order Superscalar (456).mp49.48MB
  • MP4lectures\\05-Superscalar1\\/Computer Architecture 4.4 L4S5 Fetch Logic and Alignment (1101).mp419.12MB
  • MP4lectures\\06-Superscalar3-and-Exceptions\\/Computer Architecture 5.0 L5S1 ba<x>seline Superscalar and Alignment (416).mp48.49MB
  • MP4lectures\\06-Superscalar3-and-Exceptions\\/Computer Architecture 5.1 L5S2 Interrupts and Bypassing (1213).mp423.66MB
  • MP4lectures\\06-Superscalar3-and-Exceptions\\/Computer Architecture 5.2 L5S3 Interrupts and Exceptions (2925).mp457.23MB
  • MP4lectures\\06-Superscalar3-and-Exceptions\\/Computer Architecture 5.3 L5S4 Introduction to Out-of-Order Processors (3053).mp461.92MB
  • MP4lectures\\07-Superscalar3\\/Computer Architecture 6.0 L6S1 Review of Out-of-Order Processors (326).mp46.86MB
  • MP4lectures\\07-Superscalar3\\/Computer Architecture 6.1 L6S2 I2O2 Processors (1958).mp438.79MB
  • MP4lectures\\07-Superscalar3\\/Computer Architecture 6.2 L6S3 I2O1 Processors (2844).mp4161.88MB
  • MP4lectures\\07-Superscalar3\\/Computer Architecture 6.3 L6S4 IO3 Processors (1623).mp432.01MB
  • MP4lectures\\07-Superscalar3\\/Computer Architecture 6.4 L6S5 IO2I Processors (431).mp48.07MB
  • MP4lectures\\08-Superscalar4\\/Computer Architecture 7.0 L7S1 Speculation and Branch (1437).mp429.08MB
  • MP4lectures\\08-Superscalar4\\/Computer Architecture 7.1 L7S2 Register Renaming Introduction (1108).mp463.30MB
  • MP4lectures\\08-Superscalar4\\/Computer Architecture 7.2 L7S3 Register Renaming with Pointers to IQ and ROB (2454).mp4141.77MB
  • MP4lectures\\08-Superscalar4\\/Computer Architecture 7.3 L7S4 Register Renaming with Values in IQ and ROB (1214).mp467.58MB
  • MP4lectures\\08-Superscalar4\\/Computer Architecture 7.4 L7S5 Memory Disambiguation (949).mp455.91MB
  • MP4lectures\\09-VLIW1\\/Computer Architecture 8.0 L8S1 Limits of Out-of-Order Design Complexity (1313).mp425.64MB
  • MP4lectures\\09-VLIW1\\/Computer Architecture 8.1 L8S2 Introduction to VLIW (2157).mp442.25MB
  • MP4lectures\\09-VLIW1\\/Computer Architecture 8.2 L8S3 VLIW Compiler Optimizations (2120).mp440.04MB
  • MP4lectures\\09-VLIW1\\/Computer Architecture 8.3 L8S4 Classic VLIW Challenges (818).mp415.54MB
  • MP4lectures\\09-VLIW1\\/Computer Architecture 8.4 L8S5 Introduction to Predication (951).mp419.29MB
  • MP4lectures\\10-VLIW2\\/Computer Architecture 9.0 L9S1 Scheduling Model Review (558).mp420.03MB
  • MP4lectures\\10-VLIW2\\/Computer Architecture 9.1 L9S2 Review of Predication (3048).mp473.24MB
  • MP4lectures\\10-VLIW2\\/Computer Architecture 9.2 L9S3 Predication Implementation (1006).mp423.85MB
  • MP4lectures\\10-VLIW2\\/Computer Architecture 9.3 L9S4 Speculation Execution (2602).mp449.14MB
  • MP4lectures\\10-VLIW2\\/Computer Architecture 9.4 L9S5 Dynamic Events and Clustered VLIWs (1042).mp423.22MB
  • MP4lectures\\10-VLIW2\\/Computer Architecture 9.5 L9S6 Case Study IA-Itanium (2110).mp449.11MB
  • MP4lectures\\11-Branch-Prediction\\/Computer Architecture 10.0 L10S1 Branch Cost Motivation (637).mp412.05MB
  • MP4lectures\\11-Branch-Prediction\\/Computer Architecture 10.1 L10S2 Branch Prediction Introduction (518).mp49.36MB
  • MP4lectures\\11-Branch-Prediction\\/Computer Architecture 10.2 L10S3 Static Outcome Prediction (1605).mp429.34MB
  • MP4lectures\\11-Branch-Prediction\\/Computer Architecture 10.3 L10S4 Dynamic Outcome Prediction (2912).mp4165.22MB
  • MP4lectures\\11-Branch-Prediction\\/Computer Architecture 10.4 L10S5 Target Address Prediction (1845).mp435.72MB
  • MP4lectures\\12-Advanced-Caches-1\\/Computer Architecture 11.0 L11S1 Basic Cache Optimizations (1608).mp434.49MB
  • MP4lectures\\12-Advanced-Caches-1\\/Computer Architecture 11.1 L11S2 Cache Pipelining (1416).mp428.37MB
  • MP4lectures\\12-Advanced-Caches-1\\/Computer Architecture 11.2 L11S3 Write Buffers (952).mp421.52MB
  • MP4lectures\\12-Advanced-Caches-1\\/Computer Architecture 11.3 L11S4 Multilevel Caches (1737).mp452.78MB
  • MP4lectures\\12-Advanced-Caches-1\\/Computer Architecture 11.4 L11S5 Victim Caches (604).mp458.50MB
  • MP4lectures\\12-Advanced-Caches-1\\/Computer Architecture 11.5 L11S6 Prefetching (1234).mp4148.87MB
  • MP4lectures\\13-Advanced-Caches-2\\/Computer Architecture 12.0 L12S1 Multiporting and Banking (2008).mp448.59MB
  • MP4lectures\\13-Advanced-Caches-2\\/Computer Architecture 12.1 L12S2 Software Memory Optimizations (1653).mp470.87MB
  • MP4lectures\\13-Advanced-Caches-2\\/Computer Architecture 12.2 L12S3 Non-blocking Caches (1929).mp442.11MB
  • MP4lectures\\13-Advanced-Caches-2\\/Computer Architecture 12.3 L12S4 Critical Word First and Early Restart (306).mp47.03MB
  • MP4lectures\\14-Memory-Protection\\/Computer Architecture 13.0 L13S1 Memory nagement Introduction (1304).mp432.06MB
  • MP4lectures\\14-Memory-Protection\\/Computer Architecture 13.1 L13S2 ba<x>se and Bound Registers (4).mp426.02MB
  • MP4lectures\\14-Memory-Protection\\/Computer Architecture 13.2 L13S3 Page ba<x>sed Memory Systems (2704).mp4154.80MB
  • MP4lectures\\14-Memory-Protection\\/Computer Architecture 13.3 L13S4 Translation and Protection (1437).mp433.57MB
  • MP4lectures\\14-Memory-Protection\\/Computer Architecture 13.4 L13S5 TLB Processing (1200).mp426.04MB
  • MP4lectures\\15-Vector-Processors-and-GPUs\\/Computer Architecture 14.0 L14S1 Address Translation Review (936).mp422.70MB
  • MP4lectures\\15-Vector-Processors-and-GPUs\\/Computer Architecture 14.1 L14S2 Cache and Memory Protection Interaction (2218).mp454.93MB
  • MP4lectures\\15-Vector-Processors-and-GPUs\\/Computer Architecture 14.2 L14S3 Vector Processor Introduction (1804).mp444.55MB
  • MP4lectures\\15-Vector-Processors-and-GPUs\\/Computer Architecture 14.3 L14S4 Vector Paralleli (4).mp413.84MB
  • MP4lectures\\15-Vector-Processors-and-GPUs\\/Computer Architecture 14.4 L14S5 Vector Hardware Optimizations (1852).mp441.76MB
  • MP4lectures\\15-Vector-Processors-and-GPUs\\/Computer Architecture 14.5 L14S6 Vector Software and Compiler Optimizations (554).mp411.84MB
  • MP4lectures\\16-Multithreading\\/Computer Architecture 15.0 L15S1 Reduction ScatterGather and the Cray 1 (920).mp423.46MB
  • MP4lectures\\16-Multithreading\\/Computer Architecture 15.1 L15S2 SIMD (658).mp415.43MB
  • MP4lectures\\16-Multithreading\\/Computer Architecture 15.2 L15S3 GPUs (2002).mp445.16MB
  • MP4lectures\\16-Multithreading\\/Computer Architecture 15.3 L15S4 Multithreading Motivation (733).mp416.19MB
  • MP4lectures\\16-Multithreading\\/Computer Architecture 15.4 L15S5 Course-Grain Multithreading (2616).mp459.85MB
  • MP4lectures\\16-Multithreading\\/Computer Architecture 15.5 L15S6 Simultaneous Multithreading (1253).mp430.39MB
  • MP4lectures\\17-Parallel-Programming-1\\/Computer Architecture 16.0 L16S1 T Implementation (1719).mp499.34MB
  • MP4lectures\\17-Parallel-Programming-1\\/Computer Architecture 16.1 L16S2 Introduction to Paralleli (1759).mp4101.56MB
  • MP4lectures\\17-Parallel-Programming-1\\/Computer Architecture 16.2 L16S3 Sequential Consistency (2100).mp4119.03MB
  • MP4lectures\\17-Parallel-Programming-1\\/Computer Architecture 16.3 L16S4 Introduction to Locks (0339).mp421.35MB
  • MP4lectures\\18-Parallel-Programming-2\\/Computer Architecture 17.0 L17S1 Sequential Consistency Review (348).mp48.52MB
  • MP4lectures\\18-Parallel-Programming-2\\/Computer Architecture 17.1 L17S2 Locks and Sephores (1001).mp418.90MB
  • MP4lectures\\18-Parallel-Programming-2\\/Computer Architecture 17.2 L17S3 Atomic Operations (2711).mp451.27MB
  • MP4lectures\\18-Parallel-Programming-2\\/Computer Architecture 17.3 L17S4 Memory Fences (1111).mp422.67MB
  • MP4lectures\\18-Parallel-Programming-2\\/Computer Architecture 17.4 L17S5 Dekker\s Algorithm (1413).mp428.64MB
  • MP4lectures\\19-all-Multiprocessors\\/Computer Architecture 18.0 L18S1 Locking Review (204).mp411.94MB
  • MP4lectures\\19-all-Multiprocessors\\/Computer Architecture 18.1 L18S2 Bus Implementation (1211).mp469.27MB
  • MP4lectures\\19-all-Multiprocessors\\/Computer Architecture 18.2 L18S3 Cache Coherence (1704).mp497.59MB
  • MP4lectures\\19-all-Multiprocessors\\/Computer Architecture 18.3 L18S4 Bus-ba<x>sed Multiprocessors (516).mp430.12MB
  • MP4lectures\\19-all-Multiprocessors\\/Computer Architecture 18.4 L18S5 Cache Coherence Protocols (4900).mp4249.89MB
  • MP4lectures\\20-Multiprocessor-Interconnect-1\\/Computer Architecture 19.0 L19S1 More Cache Coherence Protocols (2116).mp4119.58MB
  • MP4lectures\\20-Multiprocessor-Interconnect-1\\/Computer Architecture 19.1 L19S2 Introduction to Interconnection Networks (829).mp415.04MB
  • MP4lectures\\20-Multiprocessor-Interconnect-1\\/Computer Architecture 19.2 L19S3 Message Passing (2659).mp4135.62MB
  • MP4lectures\\20-Multiprocessor-Interconnect-1\\/Computer Architecture 19.3 L19S4 Interconnect Design (1506).mp429.01MB
  • MP4lectures\\21-Multiprocessor-Interconnect-2\\/Computer Architecture 20.0 L20S1 Networking Review (756).mp419.02MB
  • MP4lectures\\21-Multiprocessor-Interconnect-2\\/Computer Architecture 20.1 L20S2 ology (1853).mp439.92MB
  • MP4lectures\\21-Multiprocessor-Interconnect-2\\/Computer Architecture 20.2 L20S3 ology Parameters (1425).mp433.79MB
  • MP4lectures\\21-Multiprocessor-Interconnect-2\\/Computer Architecture 20.3 L20S4 Network Perfornce (1535).mp431.75MB
  • MP4lectures\\21-Multiprocessor-Interconnect-2\\/Computer Architecture 20.4 L20S5 Routing and Flow Control (2027).mp448.01MB
  • MP4lectures\\22-Large-Multiprocessors\\/Computer Architecture 21.0 L21S1 Credit ba<x>sed Flow Control (723).mp414.15MB
  • MP4lectures\\22-Large-Multiprocessors\\/Computer Architecture 21.1 L21S2 Deadlock (1009).mp418.85MB
  • MP4lectures\\22-Large-Multiprocessors\\/Computer Architecture 21.2 L21S3 False Sharing (929).mp414.88MB
  • MP4lectures\\22-Large-Multiprocessors\\/Computer Architecture 21.3 L21S4 Introduction to Directory Coherence (1255).mp422.50MB
  • MP4lectures\\22-Large-Multiprocessors\\/Computer Architecture 21.4 L21S5 Implementation (2902).mp457.06MB
  • MP4lectures\\22-Large-Multiprocessors\\/Computer Architecture 21.5 L21S6 Scalability of Directory Coherence (1331).mp462.75MB
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